Field of the Invention
The invention relates to System on Chips (SOCs), and more particularly, to a System on Chip (SOC) with a debug controller and operating method thereof.
Description of the Related Art
FIG. 1 is an exemplary diagram showing a conventional SOC 100. A SOC 100 includes a processor 110, a UART (universal asynchronous receiver/transmitter) controller 120, a SRAM 170, a DRAM controller 180 and a flash controller 190. Usually, the SOC 100 works with a separate DRAM 181 and a separate flash memory 191. The SOC 100 generally has two interfaces for debugging its embedded system, i.e., a JTAG interface for connecting to an ICE (in-circuit emulator) 160 and a UART (universal asynchronous receiver/transmitter) interface for connecting to a console 150. For example, a developer normally uses the ICE 160 via the JTAG port 140 to load programs into the embedded system, run them, step through them slowly, set execution breakpoints, and view and change data used by the system's software. However, the ICE 160 with the JTAG interface is not easy to use.
For debugging software, a simple text input/output console 150 is often sufficient. This can be handled by a simple UART connection 131 through a UART port 130 on the SOC 100 to a UART port (not shown) on the console 150 (e.g., a personal computer) so that the developer can display text messages and enter inputs using a terminal/console application. However, as any other computer system, SOCs are subject to crashes and other features of its various peripheral subsystems. In the event of a processor crash, the processor 110 stops functioning properly and thus it is impossible for the developer to collect information about the operating states of the embedded system through the UART connection and the processor 110. Accordingly, what is needed is a SOC and operating method to address the above-identified problems. The invention addresses such a need.